MediaTek Egypt is seeking a skilled and motivated digital design engineer to join our high-performance team focusing on SerDes and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs.
Key Responsibilities:
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PHY IP Architecture Planning Contribute to the architectural design of PHY IPs for high-speed interfaces such as Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY.
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RTL Design & Coding Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization.
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Front-end and Back-end Integration Handle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC.
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Cross-functional Collaboration Work closely with MAC design and Design Verification (DV) teams for system-level IP verification. Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration.
Required Qualifications:
- Bachelor’s degree in Communication and Electronics Engineering, Computer Engineering
- 2+ years’ experience in RTL and digital circuit design.
- Familiarity with front-end, back-end integration flows and EDA tools.
- Hands-on experience in PHY IP development for high-speed interfaces.
- Knowledge of DSP-based IP design techniques (e.g., CDR, CTLE, FEC, FFE, FIR, IIR).
- Solid understanding of high-speed interface standards (Ethernet SerDes, PCIe, USB, HDMI, DP, MPHY, CPHY, etc.).
Preferred Skills:
- Good problem-solving and debugging skills.
- Ability to work effectively in a team environment.
- Strong communication and documentation skills.
