Join our TeamAbout this opportunity:Do you enjoy solving the hardest problems at the intersection of RTL, timing, power, area and physical implementation? This is an opportunity to take ownership and constraint development for high-performance, low power SoC designs.
We are hiring an experienced ASIC Synthesis & PPA Engineer. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, STA & QoR closure - while also actively identifying opportunities in RTL & microarchitecture level to improve the design PPA. You will work closely with RTL design, Integration, architecture, place-and-route, and DFT teams throughout the full design cycle.
What you will do:
The skills you bring:
Why join Ericsson?At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
What happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: Sweden (SE) || Stockholm
Req ID: 790595
